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The Keysight 16800 Series is a family of eight portable logic analyzer models built to debug, validate, and optimize digital systems across a range of channel counts and performance tiers. The series spans 34, 68, 102, 136, and 204 channels, with three of the models — the 16821A, 16822A, and 16823A — adding an integrated 48-channel pattern generator so digital stimulus and response can be performed from one instrument. Each model is housed in a portable chassis with a 15-inch built-in color LCD display, with an optional touch screen, dedicated run/stop keys, and a general-purpose knob for adjusting viewing and measurement parameters.
Logic analyzers in this category are used to capture multiple digital signals simultaneously and display their timing and state relationships. Engineers use them to debug embedded systems, validate FPGA designs, characterize processor buses and memory interfaces, analyze serial communications, and verify the digital portions of mixed-signal designs. The 16800 Series datasheet specifically calls out application support for FPGA dynamic probe, digital vector signal analysis, and broad processor and bus support — covering microprocessors and microcontrollers from AMD, Analog Devices, ARM, Freescale, Intel, MIPS, Motorola, and others; FPGAs from Xilinx (Kintex 7, Virtex 7, Virtex 6, Spartan 6, Virtex 5, Virtex 4) and Altera (Cyclone IV, Stratix IV GX, Arria II GX); I/O buses including PCI, PCI Express, Serial ATA, SCSI, and Serial Attached SCSI; memory buses including DDR1, DDR2, GDDR3, Fully Buffered DIMM, and Rambus; and serial buses including Fibre Channel, I2C, IEEE-1394, USB 2.0/1.1, RS-232, CAN, and IEEE-488.
ValueTronics International, LLC has supplied new and pre-owned test and measurement instruments since 1992 from our 20,000 sq ft secure warehouse at 1675 Cambridge Drive, Elgin, Illinois. Every instrument is received, inspected, and tested in-house before shipment, and our staff is available by phone and email to answer technical and configuration questions on the 16800 Series and the broader logic analyzer category.
Keysight Technologies was formed in 2014 when Agilent Technologies separated its electronic measurement business into an independent company. Agilent had itself been spun off from Hewlett-Packard in 1999, carrying forward the test and measurement instrumentation product lines that HP had developed since 1939. Logic analyzer products that were originally branded HP or Agilent — including earlier-generation 16800 Series units — are part of this same engineering lineage and are supported under the current Keysight brand.
The 16800 Series consists of eight models that share the same chassis, display, and core acquisition architecture but differ in three primary dimensions: logic analyzer channel count, whether a 48-channel pattern generator is included, and the available state speed and memory depth options. Channel counts are 34 (16801A, 16821A), 68 (16802A, 16822A), 102 (16803A, 16823A), 136 (16804A), and 204 (16806A). The 16821A, 16822A, and 16823A are the pattern-generator-equipped variants of the 34-, 68-, and 102-channel models respectively.
All eight models include the same 4 GHz (250 ps) timing zoom with 64 K depth, the same 1.0 GHz / 500 MHz maximum timing sample rates, and the same option-selectable memory depths of 1 M, 4 M, 16 M, or 32 M samples. The differentiating performance specification across the family is state mode speed: the 34-channel models offer 250 MHz state clock rate with Option 250 only, while the 68-channel and larger models offer either 250 MHz (Option 250) or 450 MHz / 500 Mb/s (Option 500).
Each pre-owned 16800 Series model linked below is its own product page with condition-matched pricing, current configuration details, and the specific options (memory depth, state speed, and — where applicable — pattern generator) installed on the unit in our inventory. Probes, pods, and accessories are sold separately and should be specified at the time of order to ensure correct connection to the device under test.
The eight 16800 Series models scale primarily on channel count and on whether a pattern generator is integrated. The 16801A and the pattern-generator-equipped 16821A are 34-channel models limited to Option 250 (250 MHz state, 250 Mb/s). The 16802A/16822A (68 channels), 16803A/16823A (102 channels), 16804A (136 channels), and 16806A (204 channels) all support either Option 250 or Option 500 (450 MHz state clock, 500 Mb/s state data rate). For comparing specific units, the comparison table that follows shows the configured channel count, state speed option, memory depth option, and pattern generator status for each model.
Within the family, the 16821A, 16822A, and 16823A are distinguished by the integrated 48-channel pattern generator, which adds 16 M vectors of stimulus memory (8 M in full-channel mode) and supports the full range of clock and data pod logic levels listed in the datasheet (TTL, CMOS, ECL, PECL, LVPECL, LVDS, and 1.8 V / 2.5 V / 3.3 V interfaces). The 16804A and 16806A do not include the pattern generator but offer the highest channel counts (136 and 204 respectively) for wide-bus and multi-interface acquisition.
| Model | Logic Analyzer Channels | Pattern Generator Channels | Max State Clock Rate |
|---|---|---|---|
| 16822A | 68 | 48 | 450 MHz with Option 500 |
| 16801A | 34 | — | 250 MHz with Option 250 |
| 16802A | 68 | — | 450 MHz with Option 500 |
| 16803A | 102 | — | 450 MHz with Option 500 |
Additional differences in specifications beyond the few shown above are not listed here — see each model's full specifications below.
| 16800 Series Logic Analyzer — Shared Specifications | |
|---|---|
| Timing Zoom (Simultaneous state and timing, all channels, all the time) | |
| Timing analysis sample rate | 4 GHz (250 ps) |
| Time interval accuracy — within a pod pair | ± (1.0 ns + 0.01% of time interval reading) |
| Time interval accuracy — between pod pairs | ± (1.75 ns + 0.01% of time interval reading) |
| Memory depth | 64 K samples |
| Trigger position | Start, center, end, or user-defined |
| Minimum data pulse width | 1 ns |
| Other | |
| Voltage threshold | –5 V to 5 V (10 mV increments) |
| Threshold accuracy | ± 50 mV + 1% of setting |
| State (Synchronous) Analysis — Option 250 | |
| tWidth | 1.5 ns |
| tSetup | 0.5 tWidth |
| tHold | 0.5 tWidth |
| tSample range | –3.2 ns to +3.2 ns |
| tSample adjustment resolution | 80 ps typical |
| Maximum state data rate on each channel | 250 Mb/s |
| Minimum time between active clock edges | 4.0 ns |
| Minimum master-to-slave clock time | 1 ns |
| Minimum slave-to-master clock time | 1 ns |
| Minimum slave-to-slave clock time | 4.0 ns |
| Minimum state clock pulse width (single edge) | 1.0 ns |
| Minimum state clock pulse width (multiple edge) | 1.0 ns |
| Clock qualifier setup time | 500 ps |
| Clock qualifier hold time | 0 |
| Time tag resolution | 2 ns |
| Maximum time count between stored states | 32 days |
| Maximum trigger sequence speed | 250 MHz |
| Maximum trigger sequence levels | 16 |
| Trigger sequence level branching | Arbitrary 4-way if/then/else |
| State (Synchronous) Analysis — Option 500 (Available on 16802A, 16803A, 16804A, 16806A, 16822A, 16823A) | |
| tWidth | 1.5 ns |
| tSetup | 0.5 tWidth |
| tHold | 0.5 tWidth |
| tSample range | –3.2 ns to +3.2 ns |
| Maximum state data rate on each channel | 500 Mb/s |
| Minimum time between active clock edges | 2.0 ns |
| Minimum state clock pulse width (single edge) | 1.0 ns |
| Minimum state clock pulse width (multiple edge) | 2.0 ns |
| Time tag resolution | 1.5 ns |
| Maximum trigger sequence speed | 500 MHz |
| Maximum trigger sequence levels | 16 |
| Trigger sequence level branching | 2-way if/then/else |
| Memory Depth Options | |
| Option 001 | 1 M samples |
| Option 004 | 4 M samples |
| Option 016 | 16 M samples |
| Option 032 | 32 M samples |
| Timing (Asynchronous) Analysis — Conventional Timing | |
| Sample rate on all channels | 500 MHz |
| Sample rate in half channel mode | 1 GHz |
| Sample period (half channel) | 1.0 ns |
| Minimum sample period (full channel) | 2.0 ns |
| Minimum data pulse width | 1 sample period + 1.0 ns |
| Time interval accuracy | ± (1 sample period + 1.25 ns + 0.01% of time interval reading) |
| Maximum trigger sequence speed | 250 MHz |
| Maximum trigger sequence levels | 16 |
| Pattern Generator (16821A, 16822A, 16823A only) | |
| Maximum memory depth | 16 MVectors |
| Number of output channels (half channel, > 180 MHz and ≤ 300 MHz) | 24 |
| Number of output channels (full channel, ≤ 180 MHz) | 48 |
| Maximum clock (half channel) | 300 MHz |
| Maximum clock (full channel) | 180 MHz |
| Memory depth in vectors (half channel) | 16 M |
| Memory depth in vectors (full channel) | 8 M |
| Logic levels supported | 5 V TTL, 3-state TTL, 3-state TTL/CMOS, 3-state 1.8 V, 3-state 2.5 V, 3-state 3.3 V, ECL, 5 V PECL, 3.3 V LVPECL, LVDS |
| Maximum number of repeat loop invocations | 1000 |
| Maximum number of "Wait" event patterns | 4 |
| Number of input lines to define a pattern | 3 |
| Maximum width of a label | 48 bits |
| PC Characteristics |
Please review the Manufacturer's Data Sheet to verify published specifications. Feedback on this webpage is always welcome — please reach out to your Test Architect at any time for questions or concerns. Thank you, we truly appreciate you being our customer.
Model No
Keysight
Condition
Used
Manufacturer
Keysight Agilent HP
Channels
68
30+ Years in Business
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30+ Years in Business
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On-site Lab
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