Pattern Generation and Error Analysis up to 32 Gb/s
Provides a single solution for Receiver stress testing, debug and compliance
Test Gen3 and Gen4 standards including PCIe, SAS, and USB3.1 and proprietary standards
DUT handshaking capability above16 Gb/s supporting RX test requirements for loopback initiation and adaptive link training for key standards such as PCIe
Protocol-aware pattern generation and error detection supports flexible stimulus response programmability and debugging of handshaking issues.
Forward error correction (FEC) emulation option supports measurement of BER both before and after error correction for commonly used Reed-Solomon FEC codes.
Calibration and test automation software available for key standards
Pattern Generation and Error Analysis up to 32 Gb/s
Optional built-in 4-tap Tx equalization with support for interactive link training
Protocol-oriented and bit-oriented multi-chain pattern sequencing with enhanced pattern/sequence editor
User-defined detector pattern matching with stimulus-response feedback
Patented Error Location Analysis™ goes beyond BER measurement to provide insight into the sources of errors through analysis of correlations and deterministic error patterns
Optional Forward Error Correction analysis provides for simulation of post-FEC error rate based upon measured error location patterns
Integrated Eye Diagram Analysis with BER Correlation including Mask Testing, Jitter Peak, BER Contour
Optional Jitter Map Comprehensive Jitter Decomposition - with Long Pattern (i.e. PRBS-31) Jitter
Applications
Design verification including signal integrity, jitter, and timing analysis
Design characterization for high-speed, sophisticated designs
Design/Verification of high-speed I/O components and systems including DUT handshaking
Signal integrity analysis – mask testing, jitter peak, BER contour, jitter map, and forward error correction emulation