BSA7500B SyntheSys Research Analyzer Used

Supported Interfaces:

• DVI/VGA display
• USB 2.0 (4 total, 2 front, 2 rear on BSA17500A/C) 
• 1 front, 1 rear other BERTscope models
• 100 base T Ethernet LAN
• IEEE-488 (GPIB)
• Parallel Printer
• Serial RS-2 2
• PS-2 Mouse/keyboard combined connector

Certifications: 

• EU EMC Directive (CE-Marked)
• UL: Underwriters Labs 
• (US) certification 
• CSA (Canada)

Applications:

• Serial Bus Design
• Semiconductor IC Evaluation
• Jitter Tolerance Compliance Testing
• High Speed Backplane Design
• Optical Transceiver Design and Manufacturing

Error Location Capture

• Live Analysis: Continuous
• Error Logging Capacity: Max. 2 GB file size
• Error Events/Second: 10,000
• Maximum Burst Length: 32 kbits

Data/Data, Clock/Clock Amplitudes and Offsets

• Configuration: Differential Outputs, each side of pair individually settable for termination, amplitude, offset.
• Interface: DC Coupled, 50 Ω reverse terminated, APC- .5 connector. Calibration into 75 Ω selectable, other impedances by keypad entry. User-replaceable Planar Crown® adapter allows change to other connector types.
• Preset Logic Families: LVPECL, LVDS, LVTTL, CML, ECL, SCFL
• Terminations: Variable, –2 to +2V
• Pre-sets: +1.5, +1.3, +1, 0, –2 V, AC-Coupled

Clock/Data Delay

• Range: Up to 1.1 GHz:30 ns
• Above 1.1 GHz: 3 ns (Greater than 1 bit period in all cases)
• Resolution: 100 fs
• Self-Calibration: Supported – at time of measurement, when temperature or bit rate are changed, instrument will recommend a self calibration. Operation takes less than 10 seconds

External Clock Input

• Allows use of an external clock source to clock the BERTScope.
• Models equipped with stress are able to add impairments to incoming clock, including when external signal has spread spectrum clocking (SSC) in excess of 5000 ppm imposed on it.
• Frequency Range: 0.1 to 7.5 GHz
• Nominal Power: 900 mV p-p (+3 dBm)
• Maximum Power: 2.0 V p-p (+10 dBm)
• Return Loss: Better than –6 dB
• Interface: 50 Ω SMA female, DC coupled into selectable termination voltage

Jitter Insertion (BERTScope S/Si/SPG models)

• One of two jitter insertion inputs. Can be used to insert SJ, RJ, BUJ if desired.
• Frequency Range: DC to 1.0 GHz
• Jitter Amplitude Range: Up to 0.5 UI (max.)
• Input Voltage Range: 0 - 2 V p-p (+10 dBm) for normal operation 6.3 V p-p (+20 dBm) Max. non-destruct input
• Interface: SMA female 50 Ω, DC coupled into 0 V

Sub-Rate Clock Output

• BERTScope model has clock divided by 4. BERTScope S/Si/SPG models have additional capabilities.
• Frequency Range: 0.125 to 3.125 GHz (12.5 GHz BERTScope S/Si/SPG)
• Amplitude Range: 1 V p-p, nominal, centered around 0 V
• Transition Time: < 500 ps
• Interface: SMA female, 50 Ω, DC coupled into 0 V

Trigger Output

• Provides a pulse trigger to external test equipment.
• It has two modes:
• 1. Divided Clock Mode: Pulses at 1/256th of the clock rate
• 2. Pattern Mode: Pulse at a programmable position in the pattern (PRBS), or fixed location (RAM patterns) 
• Stress modulation added on models so equipped, when enabled
• Minimum Pulse Width: 128 Clock Periods (Mode 1); 512 Clock Periods (Mode 2)
• Transition Time: < 500 ps
• Jitter (p-p, data to trigger): < 10 ps, typical (BSA17500A/C)
• Output Levels: > 00 mV -p-p, center at 650 mV
• Interface: 50 Ω SMA female

Pattern Start Input

• For users wanting to synchronize patterns of multiple data streams from multiple instruments simultaneously.
• Logic Levels: LVTTL (< 0.5 V Lo, > 2.5 V hi)
• Threshold: +1.2 V typical
• Max Non-destructible Input range: -0.5 V to +5.0 V
• Minimum Pulse Width: 128 serial clock periods
• Maximum Repetition Rate: 512 serial clock periods
• Interface: SMA female, > 1 kΩ impedance into 0 V

Low Frequency Jitter Input (BERTScope S/Si/SPG models) 

• Allows use of external low frequency sinusoidal jitter source to modulate the stressed pattern generator output.
• Frequency Range: DC to 100 MHz
• Jitter Amplitude Range: Up to 1 ns
• Input Voltage Range: 0-2 V p-p (+10 dBm) for normal operation 6.3 V p-p (+20 dBm) Max. non-destruct input
• Interface: SMA female 50 Ω, DC coupled into 0 V

Page Select Input

• In A-B Page Select Mode, allows external control of pattern. Logic 1 applied to input switches to Pattern B at the next completion of Pattern A.
• Logic Levels: LVTTL (< 0.5 V Lo, > 2.5 V hi)
• Threshold: +1.2 V typical
• Max Non-destructible Input range: -0.5 V to +5.0 V
• Minimum Pulse Width: 1 pattern length
• Interface: SMA female, > 1 kΩ impedance into 0 V

Sinusoidal Interference Output (BERTScope S/Si/SPG models) 

• SI output from internal generator. Can be used to apply SI after external ISI channel.
• Frequency Range: 0.1 - 2.5 GHz
• Ouput Voltage: 0-3 V p-p
• Interface: 50 Ω SMA female, AC coupled

Low Frequency Sinusoidal Jitter Output (BERTScope S/Si/SPG models)

• To allow phasing of two BERTScopes together, in-phase or anti-phase.
• Frequency: As set for internal SJ from GUI
• Amplitude: 2 V p-p, centered at 0 V
• Interface: SMA female

Analysis Views

• Error Statistics: A tabular display of bit and burst error counts and rates.
• Strip Chart: A strip chart graph of bit and burst error rates.
• Burst Length: A histogram of the number of occurrences of errors of different lengths.
• Error Free Interval: A histogram of the number of occurrences of different error free intervals.
• Correlation: A histogram showing how error locations correlate to user-set block sizes or external Marker signal inputs.
• Pattern Sensitivity: A histogram of the number of errors at each position of the bit sequence used as the test pattern.
• Block Errors: A histogram showing the number of occurrences of data intervals (of a user-set block size) with varying numbers of errors in them

BERTScope Built-In Parametric Measurements

• All BERTScopes come with Eye Diagrams and Mask Test capabilities as standard, along with Error Analysis.
• Eye Diagram
• 280x 350 pixel waveform display
• Deep acquisition
• Automatic Measurements include:
• Rise Time
• Fall Time
• Unit Interval (Data, and also Clock)
• Eye Amplitude
• Noise Level of 1 or 0
• Eye Width
• Eye Height
• Eye Jitter (p-p and RMS)
• 0 Level, 1 Level
• Extinction Ratio
• Vertical Eye Closure Penalty (VECP)
• Dark Calibration
• Signal-to-Noise Ratio
• Vp-p, Vmax, Vmin, Crossing Levels
• Rising and Falling Crossing Level (picoseconds)
• Overshoot 0 level and 1 level

Mask Testing

• Library of standard masks e.g. XFP, or edit custom masks
• Addition of positive or negative mask margin
• Import of measured BER Contour to become process control mask
• At least 1000x the sample depth of traditional sampling oscilloscope masks is ideal for ensuring the absence of rare event phenomena

An external optical receiver may be added to the input of the BERTScope detector. Through the user interface it is easy to input and save the characteristics of the receiver. Once accomplished, relevant units on physical layer displays are changed to optical power in dBm, μW or mW. Coupling may be AC or DC, and the software steps the user through dark calibration.

For electrical signals, attenuation values can be entered to properly scale eye diagrams and measurements when external attenuators are used.

For eye diagrams and mask testing, the depth of test may be varied in manual mode; the instrument will take the specified number of waveforms then stop. The range is 2,000 to 1,000,000 bits (complete waveforms). Alternatively, the default mode is Continuous, and the eye or mask test increases in depth over time.

Error analysis is a powerful series of views that associate error occurrences so that underlying patterns can be easily seen. It is easy to focus in on a particular part of an eye diagram, move the sampling point of the BERTScope there, and then probe the pattern sensitivity occurring at that precise location. For example, it is straightforward to examine which patterns are responsible for late or early edges.